1. Field
The disclosure relates generally to data processing and more specifically to sampling instructions in multithreaded processors.
2. Description of the Related Art
Chips may contain multiple processors with multiple processor cores. Such chips may be capable of handling a large number of threads. Processor cores may have built-in performance instrumentation that monitors various performance-related events occurring during operation of the processor and the processor core. Performance instrumentation may consist of performance monitor units that provide counters, support for selecting and for routing event signals to those counters, and registers to hold sampled instruction addresses. Performance monitor units may also interrupt one or more processors in response to a condition being met. For example, interruption of a thread on a processor may be necessary in response to a counter overflow to support instruction sampling. An interrupt signal to the processor may be used to freeze a sampled instruction address register (SIAR) containing the address of an instruction that is executing at the time the trigger condition occurred, or that has recently completed execution. One sampled instruction address register is needed for each thread that has to be profiled simultaneously. In massively multithreaded processors, the amount of sampled instruction address registers may take up significant area inside the processor core area.